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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip - Computer Architecture and Design Methodologies 1st ed. 2018 edition
Zheng Wang
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip - Computer Architecture and Design Methodologies 1st ed. 2018 edition
Zheng Wang
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors.
197 pages, 80 Tables, color; 72 Illustrations, color; 32 Illustrations, black and white; XX, 197 p.
Mídia | Livros Hardcover Book (Livro com lombada e capa dura) |
Lançado | 5 de julho de 2017 |
ISBN13 | 9789811010729 |
Editoras | Springer Verlag, Singapore |
Páginas | 197 |
Dimensões | 485 g |
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