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Low Power Flash Adc: Vlsi Technology Murra Subba Reddy
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Low Power Flash Adc: Vlsi Technology
Murra Subba Reddy
In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.
| Mídia | Livros Paperback Book (Livro de capa flexível e brochura) |
| Lançado | 15 de fevereiro de 2012 |
| ISBN13 | 9783845440842 |
| Editoras | LAP LAMBERT Academic Publishing |
| Páginas | 80 |
| Dimensões | 150 × 5 × 226 mm · 137 g |
| Idioma | Alemão |