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Low Power Digital Design Using Asynchronous Logic: Moving Towards Clock-less Design Sathish Vimalraj Antony Jayasekar
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Low Power Digital Design Using Asynchronous Logic: Moving Towards Clock-less Design
Sathish Vimalraj Antony Jayasekar
The need for low power design is motivated by several factors, such as the emergence of portable systems, thermal considerations, reliability issues, and, most importantly, environmental concerns. Lots of power is wasted in an electronic device when the system is idle. This book introduces a new method of achieving low power by reducing the dependency of the clock signal in the design. It mainly focuses on obtaining low power by implementing asynchronous logic.
| Mídia | Livros Paperback Book (Livro de capa flexível e brochura) |
| Lançado | 10 de outubro de 2011 |
| ISBN13 | 9783846518441 |
| Editoras | LAP LAMBERT Academic Publishing |
| Páginas | 92 |
| Dimensões | 150 × 6 × 226 mm · 155 g |
| Idioma | Alemão |