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Architectural Optimizations in Multi-core Processors: Improving Thread-based Synchronization and Communications
Sevin Fide
Architectural Optimizations in Multi-core Processors: Improving Thread-based Synchronization and Communications
Sevin Fide
The quest for greater computational power isnever-ending. Recently, the architectural trend hasshifted from improving single-threaded applicationperformance to improving multi-threaded applicationperformance. Thus, multi-core processors have beenincreasingly popular. To achieve concurrent executionof threads on multi-core processors, applicationsmust be explicitly restructured to exploitparallelism, either by programmers or compilers. However, conventional parallel programming models mayintroduce overhead due to synchronization andcommunications among threads in multi-threadedapplications. This book presents three architecturaloptimizations to improve thread-based synchronizationand communications support in multi-core processors. Register-Based Synchronization (RBS) uses hardwareregisters efficiently to provide synchronizationsupport in multi-core processors. Prepushing is asoftware controlled data forwarding technique toprovide communications support in multi-coreprocessors. Software Controlled Eviction (SCE) improves shared cache communications by placingshared data in shared caches.
Mídia | Livros Paperback Book (Livro de capa flexível e brochura) |
Lançado | 18 de novembro de 2008 |
ISBN13 | 9783639101577 |
Editoras | VDM Verlag Dr. Müller |
Páginas | 144 |
Dimensões | 199 g |
Idioma | English |
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