Planar Double-Gate Transistor: From technology to circuit 2009 edition

Marc Notes: Includes bibliographical references and index. Brief Description: The aim of the editors here is to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary circuits. The goal is to point out how we can apply new transistor structures to come up with new cells and concepts. Jacket Description/Back: This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring. Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap. The book topics are mainly focusing on: Detailed description of specific processes that allow the optimization of the CMOS IPDGT device CMOS IPDGT modeling, both compact and physical models are presented Device characterization Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates. Table of Contents: Introduction. 1 Multiple Gate Technologies; Thierry Poiroux, Maud Vinet and Simon Deleonibus. 1.1 Introduction. 1.2. Advantages of multiple gate technologies. 1.3. Planar double gate technologies. 1.4. Non planar multiple gate technologies. 1.5. Conclusions and perspectives. References. 2 Compact Modeling of Independent Double-Gate Mosfet: a Physical Approach; Daniela Munteanu and Jean-Luc Autran. 2.1. Introduction. 2.2. Drift-diffusion Drain current modeling. 2.3. Ballistic current in the subthreshold regime. 2.4. Conclusion. References. 3 Compact Modeling of Double Gate MOSFET for IC Design; Marina Reyboz, Olivier Rozeau and Thierry Poiroux. 3.1. Introduction. 3.2. Modeling of Independent Gate MOSFET With Independent Driven Gates. 3.3. Long channel IDG MOSFET Threshold voltage based model. 3.4. Short channel effects. 3.5. Conclusion. References. 4 Low Frequency Noise in Double-Gate SOI CMOS Devices; Jalal Jomaah and Gerard Ghibaudo. 4.1. Introduction. 4.2. Low Frequency Noise Analysis. 4.3. Results and Discussions. 4.4. Conclusion. References. 5 Analog Circuit Design; Philippe Freitas, David Navarro, Ian O'Connor, Gerard Billiot, Herve Lapuyade and Jean-Baptiste Begueret. 5.1. Double Gate MOSFET In Analog Design. 5.2. Current Mirrors. 5.3. Differential Pairs. 5.4. Low Voltage OTAS. 5.5. High Speed Comparators. 5.6. Conclusion. References. 6 Logic Circuit Design With DGMOS Devices; Ian O'Connor, Ilham Hassoune, Xi Yang and David Navarro. 6.1. DGMOS characteristics and impact on digital design. 6.2. Standard cells using DGMOS. 6.3. Ultra Low Power full-adder using Double gate SOI devices. 6.4. DGMOS DEVICE based reconfigurable cells. References. 7 SRAM CircuitDesign; Bastien Giraud, Olivier Thomas, Amara Amara, Andrei Vladimirescu and Marc Belleville. 7.1. Introduction. 7.2. SRAM memories. 7.3. Double gate 6T SRAM memories. 7.4. Double gate 4T & 5T SRAM memories. References. Conclusion. Appendix. Index."